Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and optimization of MOS current mode logic for parameter variations
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
The effect of design parameters on single-event upset sensitivity of MOS current mode logic
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP
Microelectronics Journal
Nanopower subthreshold MCML in submicrometer CMOS technology
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
An efficient delay model for MOS current-mode logic automated design and optimization
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Gate-level redundancy: a new design-for reliability paradigm for nanotechnologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault-tolerant interconnect mechanism for NMR nanoarchitectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOS current mode circuits: analysis design and variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power tri-state buffer in MOS current mode logic
Analog Integrated Circuits and Signal Processing
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In this work, MOS Current Mode Logic (MCML) is analyzed for application to low power, mixed signal environments. A small MCML cell library is developed and optimized for several different performance requirements. The cells are then applied to the generation of piplelined CORDIC structures and compared with equivalent CMOS circuits. MCML CORDICs are designed which can operate from 125MHz to 310MHz with power consumption varying between 4.3mW and 18.6mW. These power results are up to 1.5 times less than CMOS CORDICs with equivalent propagation delays. Design was done in a 0.25&mrg;m standard CMOS process from ST Microelectronics.