MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Analysis and design of low-phase-noise ring oscillators
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
MOSFET Modeling and Bsim3 User's Guide
MOSFET Modeling and Bsim3 User's Guide
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Electrical and optical clock distribution networks for gigascale microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing process variation impact on replica-timed static random access memory sense timing
Integration, the VLSI Journal
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An automated optimization-based design strategy is proposed for MOS current mode logic (MCML) circuits to overcome the complexities of the design procedure. The proposed design methodology determines the values of the design variables that achieve minimum power dissipation while attaining the required performance. Furthermore, comprehensive analytical formulations of the design parameters associated with MCML circuits are presented to provide guidelines for MCML designers. The proposed design methodology has the advantages of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on MCML operation is presented. The proposed strategy is used to design two popular circuits in a 0.18 µm CMOS technology, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the circuit parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as technology scales down is investigated to highlight the importance of designing for variability in future CMOS technologies.