MOSFET modeling with SPICE: principles and practice
MOSFET modeling with SPICE: principles and practice
Design and optimization of MOS current mode logic for parameter variations
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Design and optimization of MOS current mode logic for parameter variations
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
MOS current mode circuits: analysis design and variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.