ACM SIGNUM Newsletter
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Analysis and design of low-phase-noise ring oscillators
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
MOSFET Modeling and Bsim3 User's Guide
MOSFET Modeling and Bsim3 User's Guide
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Electrical and optical clock distribution networks for gigascale microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An automated optimization-based design strategy is proposed for single-level MOS Current Mode Logic (MCML) gates to overcome the complexities of the gate design procedure. The proposed design methodology determines the values of the design variables that achieve the minimum power dissipation point while attaining the required performance. The proposed design methodology has the advantage of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on the MCML gate performance is presented. The proposed strategy is used to design two popular circuits, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the gate parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as the technology scales down is investigated.