MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Implementation of low power adder design and analysis based on power reduction technique
Microelectronics Journal
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible additional cost, and hence reduce the total system energy consumption per operation. In the proposed pipelined topology, each STSCL gate is followed by a simple cross-coupled differential pair operating as a state keeper with a very low power consumption and small area overhead. Measurement results on a 32-bit pipelined adder chain fabricated with 0.18@mm CMOS technology show that the proposed approach can achieve a significant reduction in power-delay product (PDP) down to 5fJ/stage.