MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
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In this paper, we describe and discuss the effects of design parameters such as transistor size, output voltage swing and bias current on radiation sensitivity of MOS current mode logic (MCML) type sequential elements that are used in high-speed communication systems. We have implemented latches and flip-flops in 90 nm technology and show how single-event upset can be mitigated just by adjusting particular design factors at the same clock frequency. It is shown that the critical charge needed to upset the logic state of a sequential element increases up to 5 times by increasing the bias current at the cost of more power and up to 2 times by increasing output voltage swing at the cost of more area. The effect of changing operation frequency from 500MHz to 4GHz on single-event upset is also investigated. For frequencies higher than 2 GHz, critical charge improves 1.3 times.