Low-power tri-state buffer in MOS current mode logic

Authors:
Kirti Gupta;Neeta Pandey;Maneesha Gupta
Affiliations:
Department of Electronics and Communication Engineering, Delhi Technological University, New Delhi, India;Department of Electronics and Communication Engineering, Delhi Technological University, New Delhi, India;Department of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi, India
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2013

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Abstract

In this paper, a low-power tri-state buffer in MOS current mode logic (MCML) is proposed. It offers power saving by reducing the overall current flow in the circuit during the high-impedance state. The proposed MCML tri-state buffer is simulated in PSPICE using 0.18 μm TSMC CMOS technology parameters. Its performance comparison with the existing MCML tri-state buffers indicates that the proposed tri-state buffer is power efficient than the others.