VIS Speeds New Media Processing
IEEE Micro
A Number System with Continuous Valued Digits and Modulo Arithmetic
IEEE Transactions on Computers
A high-speed energy-efficient 64-bit reconfigurable binary adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
IC Mask Design
MOS current mode circuits: analysis design and variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-delay product minimization in high-performance 64-bit carry-select adders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Digital/analog arithmetic with continuous-valued residues
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Resistive-type CVNS distributed neural networks with improved noise-to-signal ratio
IEEE Transactions on Circuits and Systems II: Express Briefs
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In this paper, design of a mixed-signal 64-bit adder based on the continuous valued number system (CVNS) is presented. The 64-bit adder is generated by cascading four 16-bit radix-2 CVNS adders. Truncated summation of the CVNS digits reduced the number of required interconnections in the system, which in turn reduced design complexity and hardware costs. This adder can perform one 64-bit, two 32-bit, four 16-bit, or eight 8-bit additions on demand for media signal processing applications. The compact and low-power and low-noise design of the adder is suitable for this type of application. The 64-bit adder designed in TSMC CMOS 0.18-µm technology, has a worst case delay of 1.5 ns, energy dissipation of about 14 pJ with the core area of 13 250µm2.