Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Low power and high performance design challenges in future technologies
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
MCM technology and design for the S/390 G5 system
IBM Journal of Research and Development
SOI technology for the GHz era
IBM Journal of Research and Development
409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Low-power mixed-signal CVNS-based 64-bit adder for media signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 485ps 64-bit parallel adder in 0.18µm CMOS
Journal of Computer Science and Technology
Performance analysis of radix-4 adders
Integration, the VLSI Journal
Fast low-power 64-bit modular hybrid adder
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18- µm partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13- µm PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.