Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

Authors:
Amaury Nève;Denis Flandre;Helmut Schettler;Thomas Ludwig;Gerhard Hellner
Affiliations:
Université Catholique de Louvain, Louvain-la-Neuve, Belgium;Université Catholique de Louvain, Louvain-la-Neuve, Belgium;IBM Entwicklung GmbH, D-71032 Böblingen, Germany;IBM Entwicklung GmbH, D-71032 Böblingen, Germany;IBM Entwicklung GmbH, D-71032 Böblingen, Germany
Venue:
Proceedings of the 2002 international symposium on Low power electronics and design
Year:
2002

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Power-delay product minimization in high-performance 64-bit carry-select adders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)

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Abstract

The paper presents the design of a 64-bit carry-select adder in Branch-Based Logic, a static design style that minimizes the internal node capacitances. This feature is used to lower the dynamic power dissipation, while maintaining good speed performances. The experimental realization of the adder demonstrates an overall delay of 720 ps while only dissipating 96 mW at 1 GHz. The fabrication is based on the 0.18 &mgr;m IBM CMOS8S2 SOI technology, which uses partially depleted transistors and copper metallization.