A high-speed energy-efficient 64-bit reconfigurable binary adder

Authors:
Stefania Perri;Pasquale Corsonello;Giuseppe Cocorullo
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Rende (CS), 87036 Italy;Department of Computer Science, Mathematics, Electronics and Transportation University of Reggio Calabria, Reggio Calabria, 89060 Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Rende (CS), 87036 Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Year:
2003

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Abstract

Datapaths for media signal processing are typically built using programmable computational elements such as adders and multipliers, which can be run-time reconfigured to operate on simple integers with 8, 16, or 32 bits of precision. In this brief, a new high-speed energy-efficient reconfigurable adder for media signal processing is presented. The proposed circuit is based on carry-propagation schemes and can be partitioned to perform one 64-, two 32-, four 16-, and eight 8-bit additions. When the Austria Mikro System (AMS) 0.35 µm 2-poly 3-metal 3.3 V CMOS (CSD) process is used to produce layout, a worst propagation delay of about 4.9 ns and an average energy dissipation of about 181 µW/MHz are obtained.