A high-speed energy-efficient 64-bit reconfigurable binary adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Variable precision arithmetic circuits for FPGA-based multimedia processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
IEEE Transactions on Computers
FPU Implementations with Denormalized Numbers
IEEE Transactions on Computers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IBM POWER6 accelerators: VMX and DFU
IBM Journal of Research and Development
Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Advances in computer hardware often have little impact until they become accessible to programmers using high-level languages. For example, the IEEE floating-point arithmetic standard provides various rounding modes and exceptions, but it is difficult ...