Variable precision arithmetic circuits for FPGA-based multimedia processors

Authors:
Stefania Perri;Pasquale Corsonello;Maria Antonia Iachino;Marco Lanuzza;Giuseppe Cocorullo
Affiliations:
Dipartimento de Elettronica, Informatica E Sistemistica (D.E.I.S.), University of Calabria, Rende 87036, Italy;Department of Computer Science, Mathematics, Electronics and Transportation, University of Reggio Calabria, Reggio Calabria 89060, Italy;Department of Computer Science, Mathematics, Electronics and Transportation, University of Reggio Calabria, Reggio Calabria 89060, Italy;Dipartimento de Elettronica, Informatica E Sistemistica (D.E.I.S.), University of Calabria, Rende 87036, Italy;Dipartimento de Elettronica, Informatica E Sistemistica (D.E.I.S.), University of Calabria, Rende 87036, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

This brief describes new efficient variable precision arithmetic circuits for field programmable gate array (FPGA)-based processors. The proposed circuits can adapt themselves to different data ward lengths, avoiding time and power consuming reconfiguration. This is made possible thanks to the introduction of on purpose designed auxiliary logic, which enables the new circuits to operate in single instruction multiple data (SIMD) fashion and allows high parallelism levels to be guaranteed when operations on lower precisions are executed. The new SIMD structures have been designed to optimally exploit the resources of a widely used family of SRAM-based FPGAs, but their architectures can be easily adapted to any either SRAM-based or antifuse-based FPGA chips.