Convex separable optimization is not much harder than linear optimization
Journal of the ACM (JACM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduling with soft constraints
Proceedings of the 2009 International Conference on Computer-Aided Design
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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With the move to deep submicron processes, the design-productivity gap has continued to widen for RTL-based design methodologies. High-level synthesis has been touted as a solution to the design-productivity gap by allowing designers to move up to a higher level of abstraction where they focus on the functionality of the circuit instead of the low level details. However, at the same time, the move to deep submicron processes has led to increased levels of process variation, which must be considered during synthesis so that the performance yield of the circuit meets design specifications. In this paper, we tackle the problem of performance yield optimization during the scheduling task of high-level synthesis. We formulate the problem of performance yield optimization for scheduling as an integer linear programming problem (ILP) and offer the following contributions: 1) a totally unimodular ILP formulation for performance yield maximization and 2) a variation-aware and layout-driven iterative algorithm for performance yield improvement. Experimental results show that we can obtain significant gain in performance yield compared to a state-of-the-art variation-aware high-level synthesis tool FastYield.