Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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Process variability greatly affects power and timing of nanometer scale CMOS circuits, leading to parametric yield loss due to both timing and power constraint violations. This parametric yield loss will continue to worsen in future technologies as a result of increasing process variations [1] and the increased importance of leakage power. Hence, statistical techniques are required to maximize parametric yield under given power and frequency constraints. Recently, much progress has been reported in the area of statistical modeling of leakage power [6] and circuit timing [2-5]. These techniques are useful in analyzing the impact of process variations on performance and power in nanometer CMOS designs. In this extended abstract, we outline the need for statistical optimization methods.