Architecting ASIC libraries and flows in nanometer era
Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Use of statistical timing analysis on real designs
Proceedings of the conference on Design, automation and test in Europe
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper we propose a new methodology, called parametric on chip variation (POCV) analysis, to determine local process variation effects on the timing of designs. The proposed methodology requires relative delay and parasitic variations of cells and interconnects, respectively. Once this information is provided, delays and arrival times are propagated to calculate slacks as a function of these relative variations. A key characteristic of the POCV analysis is that it does not require a statistical library characterization or statistical RC extraction. The POCV method has been implemented in a timing analysis software, and tested on multiple production designs on 65nm and 45nm technology nodes, including multi-million instance designs. Our observation was that compared to the existing methods, POCV removes unrealistical pessimism on the setup paths and captures risks on the hold paths, with no changes to the existing timing sign-off environment.