A parametric approach for handling local variation effects in timing analysis
Proceedings of the 46th Annual Design Automation Conference
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this paper we report a set of statistical static timing (SSTA) studies performed on a UMC test chip manufactured at 90nm process node. We employed comprehensive variation extraction techniques to prepare a complete set of input variation data for the technology node. Our studies include SSTA runs in the presence of various process variation components, comparison of SSTA results to those obtained from traditional corner flows, and statistical optimization to improve parametric yield of the design. We observed that generally traditional corner methodologies produce more pessimistic results than those obtained from the SSTA. We also noticed that it is hard to guarantee pessimism in the traditional analyses, unless all the process corner combinations are sampled.