Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Analysis of substrate thermal gradient effects on optimal buffer insertion
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Process Variations and their Impact on Circuit Operation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Current Sensing Techniques for Global Interconnects in Very Deep Submicron(VDSM) CMOS
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Towards graceful aging degradation in NoCs through an adaptive routing algorithm
Proceedings of the 49th Annual Design Automation Conference
Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach
Proceedings of the Conference on Design, Automation and Test in Europe
An MILP-based aging-aware routing algorithm for NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Repeated interconnects remain the design choice for high-performance global communication due to their clearly defined performance metrics and smooth amalgamation to the VLSI CAD flow. Simultaneous variability in process-voltage-temperature (PVT) causes interconnect performance to fluctuate from its nominal value and hence it's an essential analysis needed to decide on timing margins for global wires. Negative Bias Temperature Instability (NBTI) has emerged as the most compelling device reliability concern in deep sub-micron technologies. In this paper, we thoroughly investigate the effects on NBTI-stress on PVT-induced variability in repeated global interconnect performance. The delay-spread due to PVT can deviate by 5-12% in the presence of NBTI stress. We propose 2 schemes to mitigate NBTI-stress effects on interconnect-delay and re-align the delay-distribution with its nominal state. The 1st involves upsizing all repeaters uniformly. A 5% size increment is found to be sufficient to counter the worst-case realistic deviation in delay-spread. The 2nd is a dynamic solution which involves using an NBTI detector circuit to monitor signal activity and assess device-status over a portion of the wire and increasing the drive strength of tunable buffers in the event of NBTI-stress.