Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Generation of design guarantees for interconnect matching
Proceedings of the 2006 international workshop on System-level interconnect prediction
Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th international workshop on System level interconnect prediction
Proceedings of the 20th symposium on Great lakes symposium on VLSI
| Hi-index | 0.00 |
Global interconnects are widely acknowledged as a limiting factor in future on-chip designs. Novel interconnect driving techniques like multi-level signaling have been proposed to improve performance of on-chip interconnects. This paper presents the impact of process-induced parameter variation on multi-level signaling system for on-chip interconnects. The effects of parameter variations is analyzed by Monte Carlo simulations and parameter sensitivity analyses. Monte Carlo analyses show that the threshold voltage, effective gate length and supply voltage are the key parameters that influence interconnect delay and total average power. It also shows that the interconnect delay and total average power with multi-level signaling for 10mm line in 100nm technology are normally distributed with a standard deviation of around 7.8% and 14.55% respectively. Individual parameter sensitivity analyses show that the total average power is most influenced by threshold voltage and is least influenced by drain/source parasitic resistance and thickness of oxide. The impact of different technologies, which include 180nm, 130nm and 100nm are analyzed and it can be seen that the impact of individual device variation on delay and power reduces as technology scaled down. Yield of high performance and low power bins in 180nm technology under process variations is 30%, yield of high performance bins is 23.2% and yield of low power bins is 36.1%.