Is overlay error more important than interconnect variations in double patterning?

Authors:
Kwangok Jeong;Andrew B. Kahng;Rasit O. Topaloglu
Affiliations:
University of California, San Diego, La Jolla, CA, USA;University of California, San Diego, La Jolla, CA, USA;GlobalFoundries, Sunnyvale, CA, USA
Venue:
Proceedings of the 11th international workshop on System level interconnect prediction
Year:
2009

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Abstract

Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, mask shift-induced overlay errors introduce additional variability into interconnect coupling capacitances. An important open question is whether overlay-induced performance impacts are more significant than performance variations caused by variability in interconnects. We provide TCAD as well as chip-level analyses to determine whether overlay error should receive more attention than interconnect variations during interconnect manufacturing. We develop conclusions to help determine which component should be given more importance in specific double patterning process variants.