On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th international workshop on System level interconnect prediction
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What is double patterning lithography and its impact on nanometer design?
ACM SIGDA Newsletter
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
Proceedings of the 48th Design Automation Conference
A statistical yield optimization framework for interconnect in double patterning lithography
Microelectronics Journal
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
A polynomial time triple patterning algorithm for cell based row-structure layout
Proceedings of the International Conference on Computer-Aided Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
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As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, we present an efficient modeling of timing variation with overlay which is inevitable for DPT. Our work makes it possible to analyze timing with overlay variables. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. To verify our work, we use identical interconnects having different positions and different layout decompositions. Experimental result shows that the delay has a variation from 7.8% to 9.1% depending on their locations. The well decomposed structure shows only 2.7% delay variation.