On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Overlay aware interconnect and timing variation modeling for double patterning technology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
What is double patterning lithography and its impact on nanometer design?
ACM SIGDA Newsletter
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
E-beam lithography stencil planning and optimization with overlapped characters
Proceedings of the 2011 international symposium on Physical design
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
Proceedings of the 48th Design Automation Conference
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Optimal layout decomposition for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
A framework for double patterning-enabled design
Proceedings of the International Conference on Computer-Aided Design
DOPPLER: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing
Proceedings of the International Conference on Computer-Aided Design
WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Template-mask design methodology for double patterning technology
Proceedings of the International Conference on Computer-Aided Design
Fast and lossless graph division method for layout decomposition using SPQR-tree
Proceedings of the International Conference on Computer-Aided Design
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient layout decomposition approach for triple patterning lithography
Proceedings of the 50th Annual Design Automation Conference
Double-patterning friendly grid-based detailed routing with online conflict resolution
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A high-performance triple patterning layout decomposer with balanced density
Proceedings of the International Conference on Computer-Aided Design
Layout decomposition with pairwise coloring for multiple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this paper, we propose a multi-objective min-cut based decomposition framework for stitch minimization, balanced density, and overlay compensation, simultaneously. The key challenge of DPL is to accomplish high quality decomposition for large-scale layouts under reasonable runtime with the following objectives: a) the number of stitches is minimized, b) the balance between two decomposed layers is maximized for further enhanced patterning, c) the impact of overlay on coupling capacitance is reduced for less timing variation. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. An additional decomposition constraints for self-overlay compensation are obtained by integer linear programming(ILP). With the constraints, global decomposition is executed by our modified FM graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures.