Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Overlay aware interconnect and timing variation modeling for double patterning technology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
Frequency domain decomposition of layouts for double dipole lithography
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A polynomial time exact algorithm for self-aligned double patterning layout decomposition
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Self-aligned double patterning aware pin access and standard cell layout co-optimization
Proceedings of the 2014 on International symposium on physical design
Proceedings of the International Conference on Computer-Aided Design
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
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A spacer-type self-aligned double pattering (SADP) is a pitch-splitting sidewall image method that is a major option for sub-30nm device node manufacturing due to its lower overlay sensitivity and better process window compared to other double patterning processes, such as litho-etch-litho-etch (LELE). SADP is in production use for 1D patterns in NAND Flash memory applications but applying SADP to 2D random logic patterns is challenging. In this paper, we describe the first layout decomposition methods of SADP lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. We evaluate our technique on 22nm node industrial standard cells and logic designs. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2D layouts.