Self-Compensating Design for Focus Variation
Proceedings of the 42nd annual Design Automation Conference
Detailed placement for improved depth of focus and CD control
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Quantified Impacts of Guardband Reduction on Design Process Outcomes
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Overlay aware interconnect and timing variation modeling for double patterning technology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Double patterning technology friendly detailed routing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th international workshop on System level interconnect prediction
Proceedings of the 2009 International Conference on Computer-Aided Design
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
Proceedings of the 48th Design Automation Conference
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Role of design in multiple patterning: technology development, design enablement and process control
Proceedings of the Conference on Design, Automation and Test in Europe
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Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of "bimodal" challenges for timing analysis and optimization. We assess the potential impact of bimodal CD distribution on timing analysis and guard banding, and find that the traditional "unimodal" characterization and analysis framework may not be viable for DPL. We propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standard-cell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an integer linear programming-based maximization of "alternate" mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure "double patterning correctness" after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable engineering change order (ECO) impact. With a 45 nm library and open-source design testcases, our timing-aware recoloring and placement optimization together achieve up to 271 ps (respectively, 55.75 ns) reduction in worst (respectively, total) negative slack, and 70% (respectively, 72%) reduction in worst (respectively, total) negative slack variation, respectively.