Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Using adaptive routing to compensate for performance heterogeneity
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Software adaptation in quality sensitive applications to deal with hardware variability
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AppAdapt: opportunistic application adaptation in presence of hardware variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The value of guardband reduction is a critical open issue for the semiconductor industry. For example, due to competitive pressure, foundries have started to incent the design of manufacturing-friendly ICs through reduced model guardbands when designers adopt layout restrictions. The industry also continuously weighs the economic viability of relaxing process variation limits in the technology roadmap. Our work gives the first-ever quantification of the impact of modeling guardband reduction on outcomes from the synthesis, place and route (SP&R) implementation flow. We assess the impact of model guardband reduction on various metrics of design cycle time and design quality, using open-source cores and production (specifically, ARM/TSMC) 90nm and 65nm technologies and libraries. Our experimental data clearly shows the potential design quality and turnaround time benefits of model guardband reduction. For example, we typically (i.e., on average) observe 13% standard-cell areareduction and 12% routed wirelength reduction as the consequence of a 40% reduction in library model guardband; 40% is the amount of guardband reduction reported by IBM for a variation-aware timing methodology. We also assess the impact of guardband reduction on design yield. Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing-friendly design practices.