A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Proceedings of the 1997 international symposium on Physical design
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
Proceedings of the 48th Design Automation Conference
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
Proceedings of the 48th Design Automation Conference
Automating mathematical program transformations
PADL'10 Proceedings of the 12th international conference on Practical Aspects of Declarative Languages
A polynomial time exact algorithm for self-aligned double patterning layout decomposition
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Dealing with IC manufacturability in extreme scaling
Proceedings of the International Conference on Computer-Aided Design
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography
Proceedings of the 50th Annual Design Automation Conference
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Self-Aligned Double Patterning (SADP) is being considered for use at the 10$nm$ technology node and below for routing layers with pitches down to ~50nm because it has better LER and overlay control compared to other multiple patterning candidates. To date, most of the SADP-related literature has focused on enabling SADP-legal routing in physical design tools while few attempts have been made to address the impact SADP routing has on local, standard cell (SC) I/O pin access. In this paper, we present the first study on SADP-aware pin access and layout optimization at the SC level. Accounting for SADP-specific design rules, we propose a coherent framework that uses Mixed Integer Linear Programming (MILP) and branch and bound method to simultaneously optimize SADP-based local pin access and within-cell connections. Our experimental results show that, compared with the conventional approach, our framework effectively improves pin access of the standard cells and maximizes the pin access flexibility for routing.