Multi-center congestion estimation and minimization during placement
ICCAD '00 Proceedings of the 2000 international conference on Computer-aided design
Overlay aware interconnect and timing variation modeling for double patterning technology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Proceedings of the 2009 international symposium on Physical design
Is overlay error more important than interconnect variations in double patterning?
Proceedings of the 11th international workshop on System level interconnect prediction
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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In double patterning lithography, within-layer overlay error results in critical dimensions variability. Overlay error has been considered as a systematic source of variation; however, it is segueing into a random error for technology nodes smaller than 45-nm. Therefore, statistical design techniques should be applied to estimate and optimize the yield loss due to overlay error. In this paper, we study the impacts of overlay error on functional and parametric yields of interconnects in 32- and 22-nm technologies. A yield optimization method is applied to derive optimal width and spacing of interconnects for mentioned technologies. Experimental results show that parametric yield loss becomes more problematic in 22-nm technology node compared with the functional yield loss. Moreover, we show that DFM techniques such as wire spreading are necessary to realize the desirable parametric constraints in 22-nm node. Our analysis reveals that overlay electrical impact increases considerably in DPL in the presence of congestion.