Layout decomposition for double patterning lithography
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Overlay aware interconnect and timing variation modeling for double patterning technology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
Proceedings of the 48th Design Automation Conference
Layout decomposition for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
A novel layout decomposition algorithm for triple patterning lithography
Proceedings of the 49th Annual Design Automation Conference
An efficient layout decomposition approach for triple patterning lithography
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
A high-performance triple patterning layout decomposer with balanced density
Proceedings of the International Conference on Computer-Aided Design
Layout decomposition with pairwise coloring for multiple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Constrained pattern assignment for standard cell based triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Proceedings of the International Conference on Computer-Aided Design
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As minimum feature size keeps shrinking, and the next generation lithography (e.g, EUV) further delays, double patterning lithography (DPL) has been widely recognized as a feasible lithography solution in 20nm technology node. However, as technology continues to scale to 14/10nm, DPL begins to show its limitations and usually generates too many undesirable stitches. Triple patterning lithography (TPL) is a natural extension of DPL to conquer the difficulties and achieve a stitch-free layout decomposition. In this paper, we study the standard cell based row-structure layout decomposition problem in TPL. Although the general TPL layout decomposition problem is NP-hard, in this paper we will show that for standard cell based TPL layout decomposition problem, it is polynomial time solvable. We propose a polynomial time algorithm to solve the problem optimally and our approach has the capability to find all stitch-free decompositions. Color balancing is also considered to ensure a balanced triple patterning decomposition. To speed up the algorithm, we further propose a hierarchical algorithm for standard cell based layout, which can reduce the run time by 34.5% on average without sacrificing the optimality. We also extend our algorithm to allow stitches for complex circuit designs, and our algorithm guarantees to find optimal solutions with minimum number of stitches.