Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low-power MIMO signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Effects of process and environmental variations on timing characteristics of clocked registers
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
On the impact of manufacturing process variations on the lifetime of sensor networks
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
STEAC: a platform for automatic SOC test integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
Journal of Electronic Testing: Theory and Applications
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A fault tolerant threshold logic gate design
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parameter variation effects on timing characteristics of high performance clocked registers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks
ACM Transactions on Embedded Computing Systems (TECS)
An ANFIS based fuzzy controller for corner compensation
Analog Integrated Circuits and Signal Processing
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The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using data obtained from a 0.8 micron CMOS process. The impact of these variations and correlations on circuit operation is illustrated. Examples show that circuit delay can increase from the mean by about 100% due to crosstalk effects aggravated by process variations. Case studies emphasize the need for a tighter coupling between fabrication and circuit design and the need for new design corners based on process information.