Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Process Variations and their Impact on Circuit Operation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Combinational equivalence checking for threshold logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Evaluation and Comparison of Threshold Logic Gates
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Threshold network synthesis and optimization and its application to nanotechnologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
An efficient heuristic to identify threshold logic functions
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Threshold Logic gate is used as design abstraction for most nano devices and perceived as an alternate emerging technology to CMOS implementation. It is vulnerable to manufacturing inaccuracies that alter weight values which inadvertently affect the functionality of the gate. Hence fault tolerance should be taken in to consideration during the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extent. In this work, a fault tolerant design methodology for threshold logic gate is presented.