Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Current-Mode Threshold Logic Gates
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Threshold Logic Synthesis Tool for RTD Circuits
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Algorithm Design
Nano, quantum and molecular computing: implications to high level design and validation
Nano, quantum and molecular computing: implications to high level design and validation
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Equivalence checking of combinational circuits using Boolean expression diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Threshold network synthesis and optimization and its application to nanotechnologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A fault tolerant threshold logic gate design
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (current mode, differential mode circuits), as well as the promise they hold for the future nanoalldevices (RTDs, SETs, QCAs and other nano devices). This has generated renewed interest in the design automation community to design efficient CAD tools for threshold logic. Recently a lot of work has been done to synthesize threshold logic circuits. So far there has been no efficient method to verify the synthesized circuits. In this work we address the problem of combinational equivalence checking for threshold circuits. We propose a new algorithm, to obtain compact functional representation of threshold elements. We give the proof of correctness, and analyze its runtime complexity. We use this polynomial time algorithm to develop a new methodology to verify threshold circuits. We report the result of our experiments, comparing the proposed methodology to the naive approach. We get up to 189X improvement in the run time (23X on average), and could verify circuits that the naive approach could not.