On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Exact required time analysis via false path detection
DAC '97 Proceedings of the 34th annual Design Automation Conference
Satisfiability models and algorithms for circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
A Linear Threshold Gate Implementation in Single Electron Technology
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
A Threshold Logic Synthesis Tool for RTD Circuits
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Combinational equivalence checking for threshold logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computers
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Automatic test generation for combinational threshold logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable BDD based quantum circuits
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Efficient Boolean characteristic function for timed automatic test pattern generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated mapping for reconfigurable single-electron transistor arrays
Proceedings of the 48th Design Automation Conference
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
Functional timing analysis made fast and general
Proceedings of the 49th Annual Design Automation Conference
IEEE Spectrum
Timing verification using statically sensitizable paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Threshold network synthesis and optimization and its application to nanotechnologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path sensitization in critical path problem [logic circuit design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
Identification of Threshold Functions and Synthesis of Threshold Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On reconfigurable single-electron transistor arrays synthesis using reordering techniques
Proceedings of the Conference on Design, Automation and Test in Europe
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Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. Since threshold logic has a different mechanism in functional evaluation compared to the traditional Boolean logic, a threshold logic gate can represent a more complex function. As a result, the sensitization criterion in threshold logic circuits is also different. In this work, we propose a sensitization criterion for threshold logic circuits, and show its application to the static timing analysis problem. The experimental results show the accuracy of the proposed criterion.