The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Experiments with a performance driven module generator
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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A new approach to the false path problem in timing verifiers is presented. This approach is based on the modeling of both the logic and timing behavior of a circuit. Using the logic propagation conditions associated with each delay, efficient algorithms have been developed to find statically sensitizable paths. These algorithms simultaneously perform a longest path search and a partial verification of the sensitization of the paths. The resulting paths undergo a final and complete sensitization. The algorithms find the longest statically sensitizable path, whose length is a lower bound to the critical path length, and its associated sensitizing input vector. The algorithms can be easily modified to provide an ordered list of all the statically sensitizable paths above a given threshold. An initial analysis of the circuit by the PERT algorithm guides the critical path search and allows pruning of subgraphs that cannot lead to the solution. Results show that these techniques succeed in curbing the combinatorial explosion associated with the longest statically sensitizable path search