On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Static timing analysis of dynamically sensitizable paths
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new algorithm for third generation circuit simulators: the one-step relaxation method
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Graph Algorithms
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Statistical timing verification and delay fault detection by formal signal interaction modeling in a multi-level timing simulator
Timing verification using statically sensitizable paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
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TATOO is an industrial interactive timing analysis system evolved from recently developed false path elimination algorithms. These have been extended to perform more complex searches that facilitate the rapid survey of a network. An automatic test pattern generation mechanism which exercises the statically sensitizable paths has been developed. This forms a direct link to an electrical simulator. The critical path through a network of hundreds of gates is found, the test pattern generated, the critical path simulated, and the resulting waveforms displayed in less than two minutes.