Artificial intelligence (2nd ed.)
Artificial intelligence (2nd ed.)
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for computing the longest viable path in a combinational network
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An adaptive timing-driven layout for high speed VLSI
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An electrical optimizer that considers physical layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A new algorithm for third generation circuit simulators: the one-step relaxation method
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
CINNAMON: coupled integration and nodal analysis of MOS networks
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Graph Algorithms
Hierarchical circuit extraction with detailed parasitic capacitance
DAC '83 Proceedings of the 20th Design Automation Conference
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
EXCL: A circuit extractor for IC designs
DAC '84 Proceedings of the 21st Design Automation Conference
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips
DAC '82 Proceedings of the 19th Design Automation Conference
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator
EURO-DAC '91 Proceedings of the conference on European design automation
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
Timing verification using statically sensitizable paths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EURO-DAC '92 Proceedings of the conference on European design automation
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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