Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
ADAPTS: A digital transient simulation strategy for integrated circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
VLSI timing simulation with selective dynamic regionization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Event driven adaptively controlled explicit simulation of integrated circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A programmable hardware accelerator for compiled electrical simulation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Efficient simulation of interconnect and mixed analog-digital circuits in ACES
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An event-driven transient simulation algorithm for MOS and bipolar circuits
EURO-DAC '90 Proceedings of the conference on European design automation
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator
EURO-DAC '91 Proceedings of the conference on European design automation
WAVSTAN: waveform based variational static timing analysis
Proceedings of the conference on Design, automation and test in Europe
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The use of simulation tools to verify the behavior of integrated circuits is a well established technique for circuit design. This paper describes a novel approach for circuit simulation that promises a significant improvement over conventional methods. The algorithm involves an explicit event driven technique that seems stable even when the accuracy of the solution is relaxed, and is able to perform automatic and dynamic partitioning of the network, thus allowing the full exploitation of latency in large digital networks. Although the basic method could be generalized for any type of circuit, in this paper the scope is limited to MOS integrated circuits.