Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Area-delay optimization of programmable logic arrays
Proceedings of the fourth MIT conference on Advanced research in VLSI
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Algorithms for automatic transistor sizing in CMOS digital circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Delay reduction using simulated annealing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
P.SIZE: a sizing aid for optimized designs
EURO-DAC '92 Proceedings of the conference on European design automation
A fast and accurate characterization method for full-CMOS circuits
EURO-DAC '92 Proceedings of the conference on European design automation
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal sizing rules of CMOS circuits
EURO-DAC '91 Proceedings of the conference on European design automation
A performance analysis tool for performance-driven micro-cell generation
EURO-DAC '91 Proceedings of the conference on European design automation
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Electrical performance and area improvement are important parts of the overall VLSI design task. Given designer specified constraints on area, delay, and power, EPOXY will size a circuit's transistors and will attempt small circuit changes to help meet the constraints. In addition, the system provides a flexible framework within which to evaluate the effects of different area and electrical models, as well as different optimization algorithms. Since the sum of transistor area is a better measure of dynamic power than cell area, a more accurate area model is presented. Optimization of a CMOS eight-stage inverter chain illustrates this difference; a typical minimum power implementation is 32.3% larger than the one for minimum area. The combination of a TILOS-style heuristic and augmented Lagrangian optimization algorithm yields quality results rapidly. EPOXY'S circuit analysis is from 5 to 56 times faster than Crystal.