Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor sizing in CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An electrical optimizer that considers physical layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Algorithms for automatic transistor sizing in CMOS digital circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The Art of Computer Programming Volumes 1-3 Boxed Set
The Art of Computer Programming Volumes 1-3 Boxed Set
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Macromodeling and Optimization of Digital MOS VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
APT: an area-performance-testability driven placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay and area optimization for compact placement by gate resizing and relocation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimization of critical paths in circuits with level-sensitive latches
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
EURO-DAC '94 Proceedings of the conference on European design automation
Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Post-layout optimization for deep submicron design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Physical design CAD in deep sub-micron era
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A fast and efficient algorithm for determining fanout trees in large networks
EURO-DAC '91 Proceedings of the conference on European design automation
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a heuristic approach to the optimal selection of standard cells in VLSI circuit design. We are considering a cell library composed of several templates (3-5) for each type of cell. These templates differ in area, driving capabilities, intrinsic delay, and capacitive loading. When realizing a logically synthesized circuit, we select the best templates from the cell library to minimize the total area of the cells under delay constraints. We have found a very successful heuristic approach to attack this discrete optimization problem.Experimental results show that this approach runs very fast, with the complexity of &Ogr;(n2), and improves the results obtained from the technology mapping of misII. [15]