A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits

Authors:
Kerry S. Lowe;P. Glenn Gulak
Affiliations:
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada, M5S 1A4;Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada, M5S 1A4
Venue:
EURO-DAC '94 Proceedings of the conference on European design automation
Year:
1994

Citing 4
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Abstract