A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between

Authors:
John P. Fishburn
Affiliations:
AT&T Bell Laboratories, Murray Hill, New Jersey
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 5
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Abstract

This paper describes a heuristic for speeding up combinational logic by decreasing the logic depth, at the expense of a minimal increase in circuit size. The heuristic iteratively speeds up sections of the critical path by the use of Shannon factorization on the late input. This procedure is empirically found to be capable of reproducing or even beating several classic global optimizations: a chain of an associative operator is transformed into a tree, a ripple prefix circuit into a parallel prefix circuit, and a ripple-carry adder into a slightly smaller and faster circuit than the carry-lookahead adder.