Extreme Area-Time Tradeoffs in VLSI
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
Delay optimization of linear depth boolean circuits with prescribed input arrival times
Journal of Discrete Algorithms
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Computation-efficient parallel prefix
AIC'06 Proceedings of the 6th WSEAS International Conference on Applied Informatics and Communications
Two families of parallel prefix algorithms for multicomputers
TELE-INFO'08 Proceedings of the 7th WSEAS International Conference on Telecommunications and Informatics
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
New parallel prefix algorithms
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Proceedings of the 50th Annual Design Automation Conference
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Binary addition is the most fundamental and frequentlyused operation. A well-designed adder should be fast andsatisfy the application requirements. We propose an algorithmicapproach to generate an irregular parallel-prefix adder, whichhas minimal delay for a given profile of input signals. It cancover different topologies such as ripple-carry, carry-skip andcarry-select adders. Compared with Kogge-Stone and Brent-Kungadders, the results of the proposed approach have thesmallest output delay.