Design strategies for optimal hybrid final adders in a parallel multiplier
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
Journal of the ACM (JACM)
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
An Algorithmic Approach for Generic Parallel Adders
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
Parallel Prefix Adder Design with Matrix Representation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
An efficient parallel prefix sums architecture with domino logic
IEEE Transactions on Parallel and Distributed Systems
Implementation of recursive ling adders in CMOS VLSI
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Hi-index | 0.00 |
Two-operand binary addition is the most widely used arithmetic operation in modern datapath designs. To improve the efficiency of this operation, it is desirable to use an adder with good performance and area tradeoff characteristics. This paper presents an efficient carry-lookahead adder architecture based on the parallel-prefix computation graph. In our proposed method, we define the notion of triple-carry-operator, which computes the generate and propagate signals for a merged block which combines three adjacent blocks. We use this in conjunction with the classic approach of the carry-operator to compute the generate and propagate signals for a merged block combining two adjacent blocks. The timing-driven nature of the proposed design reduces the depth of the adder. In addition, we use a ripple-carry type of structure in the nontiming critical portion of the parallel-prefix computation network. These techniques help produce a good timing-area tradeoff characteristic. The experimental results indicate that our proposed adder is significantly faster than the popular Brent-Kung adder with some area overhead. On the adder hand, the proposed adder also shows marginally faster performance than the fast Kogge-Stone adder with significant area savings.