Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
IEEE Transactions on Computers
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic synthesis of compressor trees: reevaluating large counters
Proceedings of the conference on Design, automation and test in Europe
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A Design Method for Heterogeneous Adders
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A timing-driven hybrid-compression algorithm for faster Sum-of-Products
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compressor tree synthesis on commercial high-performance FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Faster and energy-efficient signed multipliers
VLSI Design
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