A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design strategies for optimal hybrid final adders in a parallel multiplier
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Journal of the ACM (JACM)
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
Implementing Multiply-Accumulate Operation in Multiplication Time
ARITH '97 Proceedings of the 13th Symposium on Computer Arithmetic (ARITH '97)
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
A Design Method for Heterogeneous Adders
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
IBM Journal of Research and Development
Circuit optimization using carry-save-adder cells
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Satisfying the timing constraint is the utmost concern in the integrated circuit design and it is true that most critical timing paths in a circuit cover one or more arithmetic components such as adder, subtractor, and multiplier of which addition logic is commonly involved. This work addresses the problem of redesigning the addition logic (in a form of hybrid adder) on a critical timing path to meet the timing constraint while minimally allocating the required addition logic. Unlike the conventional hybrid adder design schemes in which they assume uniform or specific patterns of input signal arrival times and minimize the latest timing of the output signals, our work extracts the required timing of each output signal as well as the input arrival times directly from the circuit and resynthesizes the addition logic by creating a customized hybrid adder that is best suited, in terms of logic area, for meeting the timing constraint of the circuit. Specifically, we propose a systematic approach of hybrid adder design exploration, basically following the principle of dynamic programming with well-controlled pruning techniques. This work is realistic and practically very useful in that it can be used as a timing optimizer to the computation-intensive circuits with a tight timing budget. We provide a set of diverse experimental data to show how much the proposed hybrid adder scheme is effective in meeting or reducing timing while maintaining the circuit area as minimal as possible.