Tight integration of timing-driven synthesis and placement of parallel multiplier circuits

• Authors: Keoncheol Shin;Taewhan Kim
• Venue: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• Year: 2004

In deep submicrometer (DSM) design, the interconnect delay becomes equally as or more important than that of logic gates. In particular, to achieve timing closure in DSM design, it is essential to consider the interconnect delay at an early stage of the synthesis process. Unfortunately, few successes of achieving a tight link of front-end synthesis to back-end layout have been reported, from a practical point of view, mainly due to the inaccuracy of predicting the layout effects during the synthesis. In this brief, we address a new approach to the problem of synthesis of parallel multiplier circuits combined with the consideration of layout effects. The approach is intended to overcome some of the limitations of the previous works, in which the effects of layout on the synthesis have either not been taken into account or considered only in local and limited ways, or the computation time is extremely large. The proposed approach refines the structure and placement of the circuit by iteratively performing two tasks. Task 1: timing-driven relocation. For a parallel multiplier circuit that was restructured at the prior iteration, we attempt to replace the modules in the structure while retaining the interconnects to find a placement with shorter timing. Task 2: timing-driven resynthesis. We attempt to restructure the interconnect topology of the placement obtained from Task 1 to further reduce the circuit timing, employing two heuristics: a modified version of timing-optimal FA-tree allocation by Stelling et al. (1996), considering interconnect delay, and a critical path-based local interconnect refinement. The iterative mechanism of the two tasks practically tightly integrates the synthesis and placement tasks so that both of the effects of placement on the results of synthesis and the effects of synthesis on the results of placement are taken into account. From experiments using a set of benchmark designs, it is shown that the approach is quite effective and efficient, producing designs with less interconnect delay over the sequential method of synthesis and placement.