Integrated algorithmic logical and physical design of integer multiplier

Authors:
Shuo Zhou;Bo Yao;Jian-Hua Liu;Chung-Kuan Cheng
Affiliations:
University of California at San Diego, La Jolla, CA;University of California at San Diego, La Jolla, CA;University of California at San Diego, La Jolla, CA;University of California at San Diego, La Jolla, CA
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 9
Cited 0

Technology Scaling Effects on Multipliers

IEEE Transactions on Computers
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis

Proceedings of the 37th Annual Design Automation Conference
High-Speed Booth Encoded Parallel Multiplier Design

IEEE Transactions on Computers - Special issue on computer arithmetic
Advanced Computer Arithmetic Design

Advanced Computer Arithmetic Design
A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach

IEEE Transactions on Computers
Simple tree-construction heuristics for the fanout problem

ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists

ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing analysis algorithm for circuits with level-sensitive latches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an integrated methodology for high-performance integer multiplier design, which combines algorithmic partial product generation, logic synthesis, and physical layout into a unified process. The interconnect delay, which dominates the performance of a multiplier, is thoroughly considered in this integration. The special structures in the multiplier are utilized to reduce the high complexity of the holistic approach. Compared with multipliers generated by a state-of-the-art tool, the timing improvements of our results are 11% for a 16-bit multiplier, and 7.5% for a 32-bit multiplier.