High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Binary multiplication Using Partially Redundant Multiples
Binary multiplication Using Partially Redundant Multiples
Limits of Scaling MOSFETs
Optimum Placement and Routing of Multiplier Partial Product Trees
Optimum Placement and Routing of Multiplier Partial Product Trees
Synthesis of integer multipliers in sum of pseudoproducts form
Integration, the VLSI Journal
Integrated algorithmic logical and physical design of integer multiplier
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Since integrated circuits were invented, fabrication engineers have been able to steadily decrease the dimensions of the devices (transistors). These reductions in the minimum feature sizes have resulted in improved performance. In addition, the dimensions of the interconnect used to connect the active transistors have also scaled. The decreasing dimensions of the physical devices causes the capacitance and resistances of the different parts of the multiplier to change. Therefore, the relative delay due to each part of the multiplier changes. In addition, the different encoding schemes used to generate the partial products and the different topologies used in the reduction of the partial products effect the total latency of the multiplier. This paper examines the effects of the smaller device dimensions on multipliers. It shows that the interconnect is becoming more important and that automatic generation of partial products provides the minimum latency for small feature sizes.