Timing optimization by restructuring long combinatorial paths

Authors:
Jürgen Werber;Dieter Rautenbach;Christian Szegedy
Affiliations:
University of Bonn, Bonn, Germany;Technical University of Ilmenau, Ilmenau, Germany;Cadence Berkeley Labs, Berkeley, CA
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

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Abstract

We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We show how to adapt this algorithm to logic optimization for timing correction at late stages of VLSI physical design and report experimental results on recent industrial chips. By restructuring long critical paths, our code achieves worst-slack improvements of up to several hundred picoseconds on top of traditional timing optimization techniques.