Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
A fast algorithm for identifying good buffer insertion candidate locations
Proceedings of the 2004 international symposium on Physical design
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Approximation algorithms for network design and facility location with service capacities
APPROX'05/RANDOM'05 Proceedings of the 8th international workshop on Approximation, Randomization and Combinatorial Optimization Problems, and Proceedings of the 9th international conference on Randamization and Computation: algorithms and techniques
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A practical repeater insertion flow
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Approximation algorithms for a facility location problem with service capacities
ACM Transactions on Algorithms (TALG)
Fast buffering for optimizing worst slack and resource consumption in repeater trees
Proceedings of the 2009 international symposium on Physical design
Binary trees with choosable edge lengths
Information Processing Letters
The repeater tree construction problem
Information Processing Letters
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We present a very fast algorithm for topology generation of repeater trees. Based on the criticality of the individual sinks, which is estimated taking their required signal arrival times and their distance from the root of the repeater tree into account, this topology connects very critical sinks in such a way as to maximize the minimum slack and to minimize wiring for non-critical sinks.We establish theoretical bounds on the optimum solution and prove that our algorithm produces results that are close to optimum with respect to slack and wirelength. Experimental results on industrial designs in 130 nm and 90 nm technologies demonstrate the excellent quality of our algorithm. Moreover, one million nontrivial repeater tree topologies are constructed in less than one minute of computing time.