Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
A place and route aware buffered Steiner tree construction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Efficient generation of short and fast repeater tree topologies
Proceedings of the 2006 international symposium on Physical design
Fast buffer insertion considering process variations
Proceedings of the 2006 international symposium on Physical design
Buffer insertion under process variations for delay minimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Buffer insertion in large circuits with constructive solution search techniques
Proceedings of the 43rd annual Design Automation Conference
Fast algorithms for slew constrained minimum cost buffering
Proceedings of the 43rd annual Design Automation Conference
A new RLC buffer insertion algorithm
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a repeater insertion flow targeted for circuit-level repeater insertion at different stages of physical synthesis. We propose how to organize circuit-level flow around the net-based dynamic programming algorithm for repeater insertion. We discuss what accuracy is required for the timing model at different stages of our flow and what stages determine the quality of the overall results. Our flow was tested on industrial designs with very high-fanout nets. It is capable of simultaneously solving the problem of fanout optimization and repeater insertion during the physical synthesis. We have achieved more than 60% reduction in repeater area without compromising timing by considering sink polarity during the topology generation and applying a set of refinement techniques.